1. Field of the Invention
The present invention relates to a semiconductor memory device for enhancing a bitline precharge time.
2. Description of the Related Art
A Dynamic Random Access Memory (DRAM) is a type of volatile semiconductor memory device that includes read and write operations. For a read operation in the DRAM, for example, once memory cells, which are connected to the same word line, are selected by a row address applied in the read operation, memory cell data stored in respective memory cells is represented as a weak electric signal through a corresponding bitline (hereinafter, referred to as “B/L”). The memory cell data represented in the B/L is sensed and amplified by a bitline sense amplifier (hereinafter, referred to as “S/A”), and then output over a ‘read operation path’ via an output buffer to a data output line.
In a write operation, once externally applied write data enters a write buffer, the write data received through the write buffer is passed through a path (opposite to the above-mentioned read operation path) and stored at a memory cell corresponding to an applied row address.
FIG. 1 is a circuit diagram illustrating a conventional art semiconductor memory device. In FIG. 1, memory cells 10 and 11 within a memory cell array and a S/A 40 are connected to each other via bitline pair BL and BLB. The bitline pair is individually coupled with isolation parts 30 and 31 and equalizers 20 and 21. Isolation parts 30 and 31 are substantially identical, thus only isolation part 30 is discussed in further detail for the sake of brevity. Isolation part 30 is composed of isolation transistors NM4 and NM5. The drain-source channels of NM4 and NM5 are each connected to a bitline BL and a complementary bitline BLB of the bitline pair. The gate terminals of NM4 and NM5 receive a common isolation control signal PISOi which electrically isolates memory cell 10 from the S/A 40. If a memory cell (such as memory cell 10) is selected from among a plurality of memory cells, the memory cell 10 is electrically connected to S/A 40 through the bitline pair BL, BLB, and the non-selected memory cell 11 (by application of isolation control signal PISOj, for example) is electrically isolated from the S/A 40.
The semiconductor memory device includes equalizers 20 and 21. Equalizers 20 and 21 are identical, thus only equalizer 20 is discussed in further detail for the sake of brevity. Equalizer 20 is composed of equalization transistors NM1, NM2 and NM3. The drain-source channels of NM1, NM2 and NM3 are individually connected to bitline BL and complementary bitline BLB. Each gate terminal of NM1, NM2 and NM3 receive an equalization control signal PEQi to equally precharge potentials of the bitline BL and complementary bitline BLB. Herewith, a precharge voltage PR can be determined as a half source voltage. The equalization transistors NM1, NM2 and NM3 are disabled in an active mode (such as a read or write operation etc.) and are enabled in a precharge mode. Therefore, once the equalization transistors NM1, NM2 and NM3 are enabled in the precharge mode, the bitline BL and complementary bitline BLB have the same voltage level.
Herewith, once isolation part 30 is driven during an active operation (e.g., read or write operation), a high voltage VPP, at a voltage level greater than an operation source voltage VCC, is applied to gate terminals of the isolation transistors NM4 and NM5. This is done in order to transfer an intact voltage at the high level (VPP) on one of the bitline BL and the complementary bitline BLB to S/A 40 without a drop in a threshold voltage of the transistors NM4 and NM5.
Since a high voltage (VPP) is applied thereto, thickness of the gate oxides of isolation transistors NM4 and NM5 is greater than thickness of gate oxides of transistors in the semiconductor memory device with gate terminals receiving VCC. This greater gate oxide thickness provides protection against a high electric field. In a MOS transistor, as the thickness of the gate oxide increases, the threshold voltage also increases, which reduces a current drive capability of the MOS transistor. Thus, in the precharge mode (e.g., not the active mode), time required to equalize a voltage level of BL and BLB increases by a difficult turn-on operation of the isolation transistors NM4 and NM5.
An explanation follows of why time for the precharge operation in the semiconductor memory device of FIG. 1 is lengthened. Referring to FIG. 1, if operation mode signals PBLSi, PBLSiB and PBLSjB in the precharge mode are individually applied as a low state, high state and high state, an equalization control signal generator 50 generates an equalization control signal PEQi at a high level. Then, a voltage level of respective gate terminals of the equalization transistors NM1, NM2 and NM3 is changed from 0V to VCC, initiating a bitline precharge operation to raise voltage levels toward a level of a half source voltage. Meanwhile, in this precharge mode, application of VPP is removed from the gate terminals of isolation transistors NM4 and NM5, and an internal supply voltage having a relatively low level, e.g., the operation source voltage VCC, is applied thereto.
Additionally in this case, a previously applied ground voltage VSS (not shown in FIG. 1) is removed from the gate terminals of isolation transistors NM6 and NM7 (connected to the non-selected memory cell 11), and the operation source voltage VCC is applied thereto. Since the isolation control signal PISOi is applied at the level of the operation source voltage VCC, an output of a gate NAN1 in an isolation control signal generator 60 responding to operation mode signals PBLSiB and PBLSjB becomes low, and each of P-type MOS transistors PM1, PM2 and PM3 and N-type MOS transistor NM11 of the isolation control signal generator 60 turn-on. In this case, with the bitline pair BL/BLB separated between memory cell 10 and S/A 40, and given that high voltage level data exists on the bitline BL, a bitline BLO3 that is physically closer to memory cell 10 than to S/A 40 is equalized faster than a bitline BLO0 that is closer to the S/A 40 than the memory cell 10. Accordingly, a gate-source voltage difference in isolation transistor NM4 is substantially low, barely exceeding a threshold voltage of the transistor. Thus, an electric potential of the bitline BLO0 adjacent to the S/A 40 is not smartly reduced toward a level of the half source voltage, but instead slowly reduces to the level of the half source voltage.
FIG. 4 illustrates bitline precharge operations of a conventional technology. Referring to FIG. 4, typically an electric potential of the bitline BLO3 reaches the precharge level, and then, after about 0.003 μs, an electric potential of the bitline BLO0 reaches the precharge level, as indicated by the long slope of the PISIO curve. Additionally, since the gate oxide of the isolation transistor NM4 is thicker in comparison with other transistors that are connected to VCC, the threshold voltage of isolation transistor NM4 is relatively high and a current drive capability of isolation transistor NM4 is relatively low. As isolation transistor NM4 receives an operation source voltage of about 1.5V in the precharge mode (e.g., instead of receiving a high voltage of about 3V), the gate-source voltage difference is very small. In other words, there is no guarantee of proper turn-on operation for isolation transistor NM4.
That is, if a difference between a voltage of the isolation control signal PISOi and a voltage of the bitline is not sufficiently greater than the threshold voltage of the isolation transistor NM4, current capacity flowing through the isolation transistor NM4 is substantially small, potentially lengthening bitline equalization time.
Conventionally, one of bitline pair BLO0 and BLBO0 nearest S/A 40 is equalized relatively late, due to the substantially small current drive capabilities of isolation transistors NM4 and NM5. Thus, overall precharge time is increased, potentially adversely affecting high speed operations in the semiconductor memory device.